1. Field of Invention
The present invention relates to a semiconductor fabrication method, and more particularly to a patterning method.
2. Description of Related Art
As the degree of integration of a memory device is getting higher, the dimension of the same is getting smaller, and the channel length becomes shorter to increase the device operation speed. However, the short channel effect is generated when the channel length is shortened to a certain extent, and the performance of the device is reduced.
In a non-volatile memory, channel regions are under word lines. To increase the channel length, one known method is to maintain the pitch but increase the line width of word lines (or reduce the gap between word lines), so as to avoid the short channel effect at the same device density. However, the line width of word lines is limited by the exposure limit dimension of a lithography process. For example, the method of forming word lines includes sequentially forming a conductive layer and a patterned photoresist layer on a substrate. The patterned photoresist layer has an opening and covers a portion of the conductive layer for forming the word lines. When each word line to be formed is wide, the opening of the patterned photoresist layer is reduced, so that photoresist scum is generated in the opening. Therefore, the process window is very narrow. Accordingly, to fabricate a wider word line without photoresist scum resulted from the narrow process window has become an important topic in the industry.